Japanese Laid-Open Patent Publication No. 2011-216740 describes an example of a wiring substrate incorporating an electronic component such as a semiconductor chip. The wiring substrate includes a core substrate having a cavity, an electronic component arranged in the cavity, and build-up layers formed on the two opposite surfaces of the core substrate. The electronic component is encapsulated in an insulative resin material that fills the cavity. The electronic component is electrically connected to wires in the build-up layers through vias formed in the build-up layers.
A method for manufacturing the wiring substrate will now be described. First, as illustrated in FIG. 15A, a cavity 90X is formed in a core substrate 90. A temporary fastening tape 91 is applied to a lower surface 90A of the core substrate 90 to close the cavity 90X, and an electronic component 92 is arranged on the tape 91 in the cavity 90X. Then, referring to FIG. 15B, vacuum lamination, vacuum hot pressing, or the like is performed to fill the cavity 90X and cover an upper surface 90B of the core substrate 90 with an insulating layer 93. Subsequently, as illustrated in FIG. 15C, the tape 91 is removed from the core substrate 90. Then, as illustrated in FIG. 15D, an insulating layer 94 is stacked on the lower surface 90A of the core substrate 90, to which the tape 91 had been attached. Laser processing, for example, is performed to form via holes VH11 and VH12 in the insulating layers 94 and 93, respectively. Subsequently, a semi-additive process, for example, is performed to form wiring layers 95 and 96. Then, a certain number of insulating layers and wiring layers are stacked on the insulating layers 94 and 93.